[ CourseBoat com ] Udemy - VSD - Physical Design Flow

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Torrent Hash :	0BE6699C7D085C3EE818BCBC06B956D04DB9D433
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Torrent Size :	1.5 GB

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Torrent File Content (62 files)

[ CourseBoat.com ] Udemy - VSD - Physical Design Flow
Get Bonus Downloads Here.url -

180 bytes

~Get Your Files Here !
01 - Physical Design Flow Overview/001 Floor-Planning Steps.mp4 -

11.94 MB

01 - Physical Design Flow Overview/001 Floor-Planning Steps_en.vtt -

14.95 KB

01 - Physical Design Flow Overview/002 Netlist Binding And Placement Optimization.mp4 -

15.2 MB

01 - Physical Design Flow Overview/002 Netlist Binding And Placement Optimization_en.vtt -

13.09 KB

01 - Physical Design Flow Overview/003 Placement Timing And Clock Tree Synthesis.mp4 -

18.28 MB

01 - Physical Design Flow Overview/003 Placement Timing And Clock Tree Synthesis_en.vtt -

12.7 KB

01 - Physical Design Flow Overview/004 Clock Net Shielding.mp4 -

14.72 MB

01 - Physical Design Flow Overview/004 Clock Net Shielding_en.vtt -

13.59 KB

01 - Physical Design Flow Overview/005 Route - DRC Clean - Parasitics Extraction - Final STA.mp4 -

22.24 MB

01 - Physical Design Flow Overview/005 Route - DRC Clean - Parasitics Extraction - Final STA_en.vtt -

12.7 KB

02 - Floorplanning/001 Utilization Factor And Aspect Ratio.mp4 -

8.85 MB

02 - Floorplanning/001 Utilization Factor And Aspect Ratio_en.vtt -

12.45 KB

02 - Floorplanning/002 Concept Of Pre-Placed Cells.mp4 -

8.84 MB

02 - Floorplanning/002 Concept Of Pre-Placed Cells_en.vtt -

13.32 KB

02 - Floorplanning/003 De-coupling Capacitors.mp4 -

11.36 MB

02 - Floorplanning/003 De-coupling Capacitors_en.vtt -

13.55 KB

02 - Floorplanning/004 Power Planning.mp4 -

12.29 MB

02 - Floorplanning/004 Power Planning_en.vtt -

15.05 KB

02 - Floorplanning/005 Pin Placement And Logical Cell Placement Blockage.mp4 -

46.24 MB

02 - Floorplanning/005 Pin Placement And Logical Cell Placement Blockage_en.vtt -

13.6 KB

03 - Placement/001 Net-list Binding And Placement.mp4 -

46.34 MB

03 - Placement/001 Net-list Binding And Placement_en.vtt -

13.18 KB

03 - Placement/002 Optimize Placement Using Estimated Wire Length And Capacitance.mp4 -

91.34 MB

03 - Placement/002 Optimize Placement Using Estimated Wire Length And Capacitance_en.vtt -

14.37 KB

03 - Placement/003 Optimize Placement Conitnued.mp4 -

86.89 MB

03 - Placement/003 Optimize Placement Conitnued_en.vtt -

12.08 KB

04 - Timing Analysis With Ideal Clocks/001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time.mp4 -

31.52 MB

04 - Timing Analysis With Ideal Clocks/001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time_en.vtt -

13.17 KB

04 - Timing Analysis With Ideal Clocks/002 Introduction To Clock Jitter and Uncertainty.mp4 -

41.02 MB

04 - Timing Analysis With Ideal Clocks/002 Introduction To Clock Jitter and Uncertainty_en.vtt -

10.65 KB

04 - Timing Analysis With Ideal Clocks/003 Setup Timing Analysis with Multiple Clocks.mp4 -

34.35 MB

04 - Timing Analysis With Ideal Clocks/003 Setup Timing Analysis with Multiple Clocks_en.vtt -

11.7 KB

04 - Timing Analysis With Ideal Clocks/004 Multiple Clock Timing Analysis And Introduction To Data Slew Check.mp4 -

72.81 MB

04 - Timing Analysis With Ideal Clocks/004 Multiple Clock Timing Analysis And Introduction To Data Slew Check_en.vtt -

12.47 KB

04 - Timing Analysis With Ideal Clocks/005 Data Slew Check.mp4 -

82.84 MB

04 - Timing Analysis With Ideal Clocks/005 Data Slew Check_en.vtt -

12.98 KB

05 - Clock Tree Synthesis And Signal Integrity/001 Clock Tree Routing And Buffering using H-Tree Algorithm.mp4 -

66.47 MB

05 - Clock Tree Synthesis And Signal Integrity/001 Clock Tree Routing And Buffering using H-Tree Algorithm_en.vtt -

12.86 KB

05 - Clock Tree Synthesis And Signal Integrity/002 Crosstalk And Clock Net Shielding.mp4 -

59.25 MB

05 - Clock Tree Synthesis And Signal Integrity/002 Crosstalk And Clock Net Shielding_en.vtt -

13.03 KB

05 - Clock Tree Synthesis And Signal Integrity/003 Static Timing Analysis With Real Clocks.mp4 -

47.73 MB

05 - Clock Tree Synthesis And Signal Integrity/003 Static Timing Analysis With Real Clocks_en.vtt -

15.91 KB

05 - Clock Tree Synthesis And Signal Integrity/004 Hold Timing Analysis Concluded.mp4 -

74.54 MB

05 - Clock Tree Synthesis And Signal Integrity/004 Hold Timing Analysis Concluded_en.vtt -

14.13 KB

05 - Clock Tree Synthesis And Signal Integrity/005 Multiple Clocks Setup Timing Analysis With Real Clocks.mp4 -

58.01 MB

05 - Clock Tree Synthesis And Signal Integrity/005 Multiple Clocks Setup Timing Analysis With Real Clocks_en.vtt -

11.38 KB

06 - Routing And Design Rule Check (DRC)/001 Introduction to Maze Routing - Lee's Algorithm.mp4 -

88.2 MB

06 - Routing And Design Rule Check (DRC)/001 Introduction to Maze Routing - Lee's Algorithm_en.vtt -

12.37 KB

06 - Routing And Design Rule Check (DRC)/002 Lee's Algorithm Conclusion.mp4 -

114.89 MB

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